1. Field of the Invention
The present invention relates to a semiconductor memory device which comprises a ferroelectric capacitor, and more particularly to a semiconductor memory device which comprises a highly integrated ferroelectric memory cell array and a method of manufacturing the same.
2. Description of the Related Art
Recent popularization of portable type devices has been accompanied by frequent use of nonvolatile memories from which no stored contents are lost even when power is cut off. In addition to a flash memory or SRAM, one such nonvolatile memory is a ferroelectric memory (FeRAM) which preserves data in a ferroelectric capacitor.
For example, a ferroelectric memory is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-244426. The ferroelectric capacitor of the document is a so-called capacitor-on-plug (COP) type capacitor as shown in FIG. 1 of the Publication. A plug is formed on one of the source and drain regions of a MOSFET which is a memory transistor, and then the ferroelectric capacitor is formed thereon.
In the case of forming the FeRAM of the afore-mentioned constitution, the following-problems may occur. First, independent processes are necessary for plug formation and capacitor formation. Second, an alignment margin is necessary between the plug and the capacitor. Because of the necessity of such a lithography margin, a limit inevitably occurs in high integration. Third, contact resistance easily becomes high due to oxidation on the contact surface between the plug and the lower electrode of the capacitor.
Thus, there has been a demand for a ferroelectric memory which can achieve high integration by minimizing the lithography margin which is necessary to form a plug and capacitor and reduce contact resistance of the plug.